1. Field of the Invention
The present invention relates generally to an improvement to the testing of integrated circuits ("ICs"), and more particularly, to an improved IC testing apparatus and method operating within an automated handler environment.
2. History of the Prior Art
Commercially-available ICs, i.e., semiconductor devices, are normally contained or packaged in a molded plastic housing having a generally rectangular, planar, box-like configuration. A typical IC package, commonly known as a "chip," includes one or more rows of evenly-spaced pins or leads extending perpendicularly from one face of the body and disposed along opposite and parallel sides of the body or, alternatively, along each side of the body. The semiconductor device may be a surface mounted device ("SMD") designed to be mounted directly on the surface of a circuit board or within a suitable receiving socket, or a dual-in-line packaged ("DIP") device intended for mounting with leads passing through the circuit board or within a suitable socket rather than for surface mounting.
Regardless of the nature of the semiconductor device or the specific manner of mounting, the reliability and functionality of the IC embodied in the device are important considerations for both manufacturers and users alike. A manufacturer, for example, may wish to inspect a production run or lot of semiconductor devices and discard those found to be defective. Additionally, the manufacturer would like to obtain a true and correct assessment of the capabilities of the device such as, for example, the maximum operating speed, which are directly related to the price the manufacturer can charge for the device. A customer, on the other hand, seeks an assurance that the device purchased from the manufacturer will perform according to manufacturer's specifications under real operating conditions.
A variety of manual and automatic apparatuses have been developed for testing the performance of a semiconductor device. In a manual testing apparatus, the operator manually places each device into a socket mounted on a test circuit board, conducts the test and then removes the device from the socket. By contrast, an automatic testing apparatus, commonly known as a "handler," includes a mechanism for automatically moving a plurality of devices, in sequence (one after the other) or in parallel (two or more together), into electrical contact with the testing board and for separating the defective devices from the fully functional devices in accordance with the test results.
The choice between a manual and an automatic testing apparatus has several implications. On the one hand, a manual testing apparatus using a socket mounted directly to the test circuit board offers an electromagnetic environment which approaches actual use. However, a manual test is both slow and time-consuming and requires frequent replacement of the sockets which tend to wear out rapidly. On the other hand, handlers have gained wide acceptance in the industry precisely because of their speed. Unfortunately, a handler tests the semiconductor device at a relatively remote location from the test circuit and/or the test measurement instrumentation and, therefore, in a suspect environment. To illustrate the importance of proximity of the semiconductor device to the test circuit, it is known, for example, that merely changing the lead length in a test situation by as little as a quarter inch from the actual use situation may lead to significant changes in the electrical response of the device under test.
In a typical handler, the device is momentarily brought to rest at a test station where a set of contacts are flexed or compressed by push bar action into electrical contact with the pins of the device. The contacts are usually a part of a probe or contactor assembly having an insulating base member on which the contacts are mounted. The contactor, therefore, establishes a signal path or link between the device and the testing apparatus. To determine whether a device is defective or functional, a series of test signals having a known response is generated by the testing apparatus and delivered by the contactor to the device. The response at some or all of the pins is then measured and compared to the expected response. If the results of the test do not match the predetermined responses, the device is considered to be defective or of an inferior performance grade, and may then be disposed of as appropriate. As explained below, however, this testing arrangement is plagued by a host of problems which undermine the integrity of the test itself.
One such problem arises from the inherent inductance of the contacts of the contactor. During a test, the test signal travelling through the contactor encounters an inductive reactance which is a function, in part, of the frequency of the test signal being applied. The test signal is usually "fast-rising," i.e, characterized by a very steep, step-like increase in voltage level of five (5) volts per nanosecond, for example. With the aid of Fourier analysis, such a test signal may be represented as a series of superimposed sine waves having frequencies which lie within a wide range or bandwidth, e.g. 0-300 MHz, and including very high frequency components. Since the inductive reactance of the contactor is proportional to the frequency of the test signal, a high test signal frequency implies a high inductive reactance. As is well known in the art, a high reactance produces distortions and reflections which degrade the quality and accuracy of the test. A description of various contactors directed to overcoming this problem may be seen in U.S. Pat. Nos. 4,689,556 and 4,747,784, both to Cedrone, which disclose improved characteristic impedance or generally frequency insensitive contactor assemblies for testing semiconductor devices with fast rising signals.
A related problem to inductive reactance is the presence of ground or power supply noise, i.e., changes in the reference voltage caused by current surges during the test procedure. It is well known in the field of microelectronics that high frequency operation, particularly the switching of integrated circuits, can result in transient energy being coupled into the power supply circuit of a device under test. To illustrate, a change in the state of a device, e.g., conducting to non-conducting, during a test may produce a transient current surge in the range of 20 milli-amperes per nanosecond. Such a surge may, in turn, cause the ground reference voltage of the device to change by one volt or more thereby distorting test measurements referenced to ground and leading to the false rejection of devices which are not defective and which would otherwise be considered acceptable or, alternatively, to the false acceptance of actually defective devices.
Heretofore, in the use but not the testing of semiconductor devices, the decoupling of undesired high frequency noise or interference from the power supply has been accomplished by connecting one or more decoupling capacitors between the power and ground leads of a semiconductor device. Various connection schemes have been devised for this purpose. According to one such scheme, a capacitor is mounted on a multilayer printed circuit board ("PCB") having plated-through holes which are used to connect the capacitor to the internal power and ground planes which are, in turn, connected to the power and ground leads of the semiconductor device. In another scheme, which suffers from the disadvantage of higher inductance, the decoupling capacitor interconnects to the power and ground leads of the semiconductor device via traces on either a multilayer or double-sided PCB. The advantages and disadvantages of the foregoing and other decoupling techniques are discussed in U.S. Pat. No. 4,734,819 to Hernandez et al. which generally discloses the use of a decoupling capacitor specifically sized and configured for mounting directly over a "leadless" surface mount semiconductor device, or under a "leaded" surface mount semiconductor device, and between the downwardly extending pins.
The use of decoupling capacitors in the testing of semiconductor devices has been far less effective than in actual operation where the decoupling capacitor may be positioned immediately adjacent to the semiconductor device on the PCB. Because of physical constraints in the testing environment, particularly the construction of the contactor, a decoupling capacitor could not be located sufficiently close to the semiconductor device undergoing testing to be equally effective in reducing noise. Specifically, it is known that a decoupling capacitor is not effective if located at a distance greater than a quarter inch from the device being tested. The configurations of prior art contactors have, however, precluded the location of decoupling capacitors within that critical distance. Furthermore, the construction of many prior contactors rendered the decoupling capacitors difficult to reach and sometimes completely inaccessible for repair or replacement. An attempt at overcoming some of these difficulties may be seen in U.S. Pat. No. 4,668,041 to La Komski et al. which discloses the use of pogo pins as contactors in a series of plates which together act as a decoupling capacitor.
Notwithstanding the improvements and solutions proposed in the prior art, the gap between the semiconductor device test environment and actual operating conditions continues to widen. While, as mentioned above, contactors have been developed with a view to minimizing the uncertainties introduced at the handler test station, the need for bridging the gap persists. Similarly, as the use of new and improved decoupling capacitors increases in actual operation, the need to duplicate their effectiveness during testing becomes more pronounced. While some have proposed the inclusion of decoupling capacitors inside a packaged semiconductor device, the scarcity of "real estate" or space, i.e., the packaging density, within the device and the diverging needs of customers militate against such a solution. In particular, even if the internal layout of the device permits the addition of decoupling capacitors to meet the requirements of a customer for whom high speed is the primary consideration, other, more cost-sensitive customers may not be willing or able to pay the higher price likely to be charged for such a package.
The present invention has been developed with the above and other engineering and economic considerations in mind. In general terms, the present invention provides a necessary tool designed to enhance the integrity and increase the accuracy of conventional IC testing apparatuses. More specifically, the present invention is particularly suited for the testing of semiconductor devices equipped with external contacts in addition to pins such as, for example, the decoupling "capacitor pads" described immediately below.
To facilitate the direct connection of decoupling capacitors to packaged semiconductor devices or chips for purposes of actual use, many manufacturers have recently begun to provide metallic capacitor pads across the top surface of the semiconductor device packages they manufacture. A typical capacitor pad consists of a pair of rectangular-shaped gold foils, one of which connects to the power plane and the other to the ground plane inside the semiconductor device package. A small surface mount capacitor, commonly known as a "chip capacitor," may be easily connected to the semiconductor device by, for example, soldering the capacitor to one of the capacitor pad pairs or by using conductive adhesives.
The availability of chip capacitor pads which can readily accommodate decoupling capacitors promotes a reduction in the length of the signal path and the value of the impedance which would otherwise be encountered were the signal or transient noise to travel from the semiconductor device through the PCB and to the decoupling capacitor as generally required in conventional or prior art decoupling arrangements. Manufacturers of semiconductor devices, however, are reluctant to indiscriminately impose on all their customers the additional costs associated with connecting decoupling capacitors to their chip capacitor pads. Such connection, therefore, is usually left to the individual customer who intends, for example, to use the semiconductor device in a system which has a low tolerance for noise or otherwise requires superior performance, and is not made, as a matter of course, at the factory.
Hence, while the customer may use a semiconductor device with decoupling capacitors directly connected to the capacitor pads, the manufacturer tests the same semiconductor device without the benefit of such decoupling capacitors and, thus, in a testing environment which is significantly different than the operating environment. As previously mentioned, the physical constraints of a conventional handler environment, including a conventional contactor, prevent the placement of a decoupling capacitor within an effective distance from the semiconductor device being tested. Consequently, a mechanism is needed to temporarily connect decoupling capacitors to the chip capacitor pads during testing so as to closely replicate actual operating conditions and fairly evaluate the expected performance of the semiconductor device when used in a customer's circuit.
It is, therefore, an object of the present invention to provide an improved testing apparatus and method within a handler environment which includes a mechanism for converging the measurements taken at the test station with the responses observed in actual operation.
Another object of the present invention is to provide a controlled electromagnetic testing environment which closely simulates actual use conditions.
Yet another object of the present invention is to provide a testing apparatus and method which allow for the convenient connection and disconnection of electrical or electronic components to a semiconductor device under test.
A further object of the present invention is to provide a testing environment which may be readily adapted to the requirements of the test.